The task of speeding up a successive approximation (SAR) A/D converter is to reduce the power consumption of a driver for driving a capacitive D/A converter. The cause for an increase in power consumption is nothing less than the necessity of shortening the settling time of the capacitive D/A converter along with the speeding up. In response to this task, there has been proposed a successive-approximation A/D converter based on a non-binary conversion algorithm. This A/D converter adopts a system in which a comparison voltage of A/D conversion is given redundancy in each conversion cycle. By having redundancy, the A/D converter is capable of making corrections in later digital processing even if settling is more or less insufficient.
In A/D conversion based on a non-binary algorithm, a radix is 2 or smaller. Accordingly, whereas a resolution of N bits can be obtained by N cycles of A/D conversion in a binary algorithm, the number of cycles larger than N is required in the case of the non-binary algorithm, in order to obtain a resolution of N bits. An error margin of the comparison voltage becomes larger in proportion to the amount of redundancy. Likewise, the number of conversion cycles increases with an increase in the amount of redundancy. Accordingly, the non-binary algorithm is disadvantageous in that an error tolerance in the algorithm decreases in contrast to a given amount of redundancy.
The non-binary algorithm is also disadvantageous in that a digital signal processing circuit needs to be provided in the A/D converter since the result of A/D conversion has to be converted to a binary system.